Intel Tulsa & L3 16MB

[ced]

http://www.realworldtech.com/includes/images/articles/ISSCC06-Tulsa-Fig-1.gif

http://www.realworldtech.com/page.cfm?ArticleID=RWT021906030756

[Daniel]

16MB L3 cache won't make a difference if the latency is still extremely high, as was the case with the NetBurst architecture.

Btw, the Tulsa is a quad-core(dual dual-core) processor. It's not coming out til Q4 of 2007.

[niv]

Yes it will, registers can be used for storing program code (chip-specific instructions). The speed of memory close to the CPU still far exceeds that on the bus. That and since chips are getting faster, and more memory becomes available, one can spend less time optimizing and more time designing logic that will handle it well.

Remember, latency, both as time and phase, are functions of the distance away from the chip. If you're talking RAM, that's a distance of an order of magnitude higher.